1. Field of the Invention
The present invention generally relates to data encryption and, more particularly, to methods and apparatus for reducing latency associated with selectively encrypting portions of data.
2. Description of the Related Art
A system on a chip (SOC) generally includes one or more integrated processor cores, some type of embedded memory, such as a cache memory, and peripheral interfaces, such as memory control components and external bus interfaces, on a single chip to form a complete (or nearly complete) system.
As part of an enhanced security feature, some SOCs encrypt some portions of data prior to storing it in external memory. Adding such encryption to an SOC may add valuable benefits, such as preventing a hacker from obtaining instructions of a copyrighted program, such as a video game, or data that may be used to determine such instructions through reverse engineering. However, adding encryption typically impacts system performance, as conventional encryption schemes typically stream both data that is to be encrypted and data that is not to be encrypted (non-encrypted data) through a common sequential data path. As a result, non-encrypted data is typically suffers the same latency as encrypted data.
This latency may add significant delay to the storing of non-encrypted data. In addition, this latency may prevent the subsequent storage of non-encrypted data while previous data is being encrypted. Accordingly, what is needed is a mechanism to minimize performance impacts on non-encrypted data caused by encryption latency.